Parallel load shift register using j-k flip-flops.
Shift Registers digital lab help
Serial Load Shift Register using D-type Flip-Flops.
Enter the following circuit (Fig. 1) into Electronics Workbench, adding any necessary components to enable the flip-flops to be:
Clear the registers by momentarily taking the clear input low.
Set the clock to logic ‘0’, and
Parallel Load Shift Register using J-K Flip-Flops.
loaded with parallel data using the pre-set and clear inputs
observe the Q outputs
Disconnect the XOR gate input from output of gate D and connect it to the output of gate C. Repeat step 3, and comment on your observations.
Clock Pulse |
QA |
QB | QC | QD | XOR connected |
|---|---|---|---|---|---|
| 0 | 1 | 1 | 1 | 1 | |
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Universal Shift Register IC device- 74LS194
Simulate a shift register based on the 74LS194 Universal Shift Register IC. The pin connections and mode operation switches are shown below.
Serial in – Parallel out
Clear the register.
Set the parallel inputs ABCD to 0000
(d) Apply four clock pulses and confirm correct operation.
4. To shift left. Proceed as 3 above, setting and inhibiting the correct inputs. Confirm correct operation.
Applying further clock pulses causes nothing to happen. Why is this?
4. Set to Shift Right and apply four clock pulses. Note the movement of data through the register.
